In producing and manufacturing memory devices such as DRAMs, a production test usually occurs whose purpose is to ensure that a memory cell in the array can receive and hold data. It is typical to test the DRAM by operating it at a long Row Address Strobe (RAS) cycle time, such a RAS cycle of 10 microseconds, and attempting to write data of a voltage logic level "1" into an addressed memory cell towards the end of the RAS cycle. In a good DRAM, the logic level "1" can be written into the addressed memory cell and will remain there so that it is read when that memory cell is next addressed. As the DRAM size increases, from 1 megabit to 4 megabit, and to VLSI DRAMs of 16 megabits (where more than 16 million memory cells are contained on a single DRAM chip), the time it takes to perform this test for the entire DRAM array increases. For instance, in a 16 megabit DRAM operating on a RAS cycle of 10 microseconds, it takes approximately 160 seconds to access every memory cell. This large amount of time to test every DRAM is unacceptable in a production enviornment manufacturing numerous DRAMs.
Exemplary of the type of defect the above test reveals is voltage leakage. Voltage leakage can prevent the the logic "1" from being written into the memory cell. Leakage can also cause the data stored in the memory cell at the logic "1" level to decrease so that the addressed memory cell contains incorrect data.
An oxide defect in a transfer transistor that connects a storage capacitor to a bit line is an example of one type of leakage yielding defect that may occur in a DRAM. Another type of leakage yielding defect that may occur is a high resistance polyfilament short between two word lines. If the resistance is large, for example on the order of about 2 megaohms and higher , it may take quite a bit of time for the short to exhibit itself as voltage on the word line gradually leaks away.
It is known in the art for DRAM design that boosted wordlines advantageously increase the charge stored on the storage capacitors . DRAMs having boosted wordlines are described in U.S. Pat. Nos. 4,533,834 and 4,748,349, both to McAlexander, White, and Rao and both assigned to Texas Instruments Incorporated. These 64K DRAM devices use an active pull-up circuit and boot strapping to allow a logic "1" level of essentially Vdd to be stored in a storage capacitor. The basic concept of boosting wordlines may also advantageously be incorporated into VLSI DRAM design such as in the case of a 16 megabit DRAM.
When VLSI DRAMS having boosted word lines are produced, the maximum logic "1" that may be written into a storage cell is the level to which the bit lines are restored. If a word line has leakage on it, the maximum logic "1" that may be written into the storage cell is reduced. For example, assume this restore level has a value of about +3.3 v, a typical value for 16 megabit DRAMs, and that the word lines are boosted to about +5.O v. If a word line has leakage, the voltage on it will fall below +5.0 v. Assume that a word line leaks down to about +3.5 v. At this level, if the DRAM is tested during the RAS cycle above described, the maximum logic "1" that can be written to an addressed memory cell on that word line will only be about +2.3 v. As those knowledgeable in the art of DRAM design are aware, this is a dangerously low logic "1" level and can cause problems. If the wordline leakage is severe enough, it becomes impossible to write a logic level "1" into a memory cell towards the end of the RAS cycle.
It is an object of this invention to detect voltage leakage in the word lines and in the memory cells, through their transfer transistor devices, of memory devices.
It is a further object of this invention to increase the speed at which DRAMs may be tested for high resistance leakage.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.